tl/f/6367 dm54ls107a/dm74LS107a dual negative-edge-triggered master-slave j-k flip-flops with clear and complementary outputs june 1989 dm54ls107a/dm74LS107a dual negative-edge- triggered master-slave j-k flip-flops with clear and complementary outputs general description this device contains two independent negative-edge-trig- gered j-k flip-flops with complementary outputs. the j and k data is processed by the flip-flops on the falling edge of the clock pulse. the clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. the data on the j and k inputs may change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated. a low logic level on the clear input will reset the outputs regardless of the logic levels of the other inputs. connection diagram dual-in-line package tl/f/6367 1 order number dm54ls107aj, dm54ls107aw, dm74LS107am or dm74LS107an see ns package number j14a, m14a, n14a or w14b function table inputs outputs clr clk j k q q lxxxlh h v llq 0 q 0 h v hl h l h v lh l h h v h h toggle hhxxq 0 q 0 h e high logic level x e either low or high logic level l e low logic level v e negative going edge of pulse. q 0 e the output logic level before the indicated input conditions were established. toggle e each output changes to the complement of its previous level on each falling edge of the clock pulse. c 1995 national semiconductor corporation rrd-b30m105/printed in u. s. a.
absolute maximum ratings (note) if military/aerospace specified devices are required, please contact the national semiconductor sales office/distributors for availability and specifications. supply voltage 7v input voltage 7v operating free air temperature range dm54ls b 55 cto a 125 c dm74ls 0 cto a 70 c storage temperature range b 65 cto a 150 c note: the ``absolute maximum ratings'' are those values beyond which the safety of the device cannot be guaran- teed. the device should not be operated at these limits. the parametric values defined in the ``electrical characteristics'' table are not guaranteed at the absolute maximum ratings. the ``recommended operating conditions'' table will define the conditions for actual device operation. recommended operating conditions symbol parameter dm54ls107a dm74LS107a units min nom max min nom max v cc supply voltage 4.5 5 5.5 4.75 5 5.25 v v ih high level input voltage 2 2 v v il low level input voltage 0.7 0.8 v i oh high level output current b 0.4 b 0.4 ma i ol low level output current 4 8 ma f clk clock frequency (note 2) 0 30 0 30 mhz f clk clock frequency (note 3) 0 25 0 25 mhz t w pulse width clock high 20 20 ns (note 2) clear low 25 25 t w pulse width clock high 25 25 ns (note 3) clear low 30 30 t su setup time (note s1&2) 20 v 20 v ns t su setup time (note s1&3) 25 v 25 v ns t h hold time (note s1&2) 0 v 0 v ns t h hold time (note s1&3) 5 v 5 v ns t a free air operating temperature b 55 125 0 70 c note 1: the symbol ( v ) indicates the falling edge of the clock pulse is used for reference. note 2: c l e 15 pf, r l e 2k x ,t a e 25 c and v cc e 5v. note 3: c l e 50 pf, r l e 2k x ,t a e 25 c and v cc e 5v. electrical characteristics over recommended operating free air temperature range (unless otherwise noted) symbol parameter conditions min typ max units (note 1) v i input clamp voltage v cc e min, i i eb 18 ma b 1.5 v v oh high level output v cc e min, i oh e max dm54 2.5 3.4 v voltage v il e max, v ih e min dm74 2.7 3.4 v ol low level output v cc e min, i ol e max dm54 0.25 0.4 voltage v il e max, v ih e min dm74 0.35 0.5 v i ol e 4ma, v cc e min dm74 0.25 0.4 i i input current @ max v cc e max, v i e 7v j, k 0.1 input voltage clear 0.3 ma clock 0.4 2
electrical characteristics over recommended operating free air temperature range (unless otherwise noted) (continued) symbol parameter conditions min typ max units (note 1) i ih high level input v cc e max j, k 20 current v i e 2.7v clear 60 m a clock 80 i il low level input v cc e max j, k b 0.4 current v i e 0.4v clear b 0.8 ma clock b 0.8 i os short circuit v cc e max dm54 b 20 b 100 ma output current (note 2) dm74 b 20 b 100 i cc supply current v cc e max (note 3) 4 6 ma switching characteristics at v cc e 5v and t a e 25 c (see section 1 for test waveforms and output load) from (input) r l e 2k x symbol parameter to (output) c l e 15 pf c l e 50 pf units min max min max f max maximum clock 30 25 mhz frequency t plh propagation delay time preset 20 24 ns low to high level output to q t phl propagation delay time preset 20 28 ns high to low level output to q t plh propagation delay time clear 20 24 ns low to high level output to q t phl propagation delay time clear 20 28 ns high to low level output to q t plh propagation delay time clock to 20 24 ns low to high level output q or q t phl propagation delay time clock to 20 28 ns high to low level output q or q note 1: all typicals are at v cc e 5v, t a e 25 c. note 2: not more than one output should be shorted at a time, and the duration should not exceed one second. for devices, with feedback from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where v o e 2.25v and 2.125v for dm54 and dm74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. this is very useful when using automatic test equipment. note 3: with all inputs open, i cc is measured with the q and q outputs high in turn. at the time of measurement the clock is grounded. 3
physical dimensions inches (millimeters) 14-lead ceramic dual-in-line package (j) order number dm54ls107aj ns package number j14a 4
physical dimensions inches (millimeters) (continued) 14-lead small outline molded package (m) order number dm74LS107am ns package number m14a 14-lead molded dual-in-line package (n) order number dm74LS107an ns package number n14a 5
dm54ls107a/dm74LS107a dual negative-edge-triggered master-slave j-k flip-flops with clear and complementary outputs physical dimensions inches (millimeters) (continued) 14-lead ceramic flat package (w) order number dm54ls107aw ns package number w14b life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or 2. a critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. national semiconductor national semiconductor national semiconductor national semiconductor corporation europe hong kong ltd. japan ltd. 1111 west bardin road fax: ( a 49) 0-180-530 85 86 13th floor, straight block, tel: 81-043-299-2309 arlington, tx 76017 email: cnjwge @ tevm2.nsc.com ocean centre, 5 canton rd. fax: 81-043-299-2408 tel: 1(800) 272-9959 deutsch tel: ( a 49) 0-180-530 85 85 tsimshatsui, kowloon fax: 1(800) 737-7018 english tel: ( a 49) 0-180-532 78 32 hong kong fran 3 ais tel: ( a 49) 0-180-532 93 58 tel: (852) 2737-1600 italiano tel: ( a 49) 0-180-534 16 80 fax: (852) 2736-9960 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications.
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